A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n−1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n−1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n−1.