US Patent 7987398 Reconfigurable device

Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.