US Patent 8037382 Multi-mode programmable scan flop

A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled between the functional flop and the scan flop. The latch circuit includes one or more mode signal inputs to enable selection of an operating mode. In a first mode, the latch circuit is configured to enable the functional flop to provide a data signal to the scan flop. In a second mode, the latch circuit is configured to enable the scan flop to provide a data signal to the functional flop. In a third mode, the latch circuit is configured to provide a feedback path in order to feed back to the functional flop a signal generated by the functional flop.