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US Patent 8039179 Integrated circuit layout design

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
December 29, 2010
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Date of Patent
October 18, 2011
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Patent Application Number
12980764
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Patent Citations Received
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US Patent 11664237 Semiconductor device having improved overlay shift tolerance
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US Patent 12009202 Using a self-assembly layer to facilitate selective formation of an etching stop layer
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US Patent 11764286 Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
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US Patent 11748540 Method and structure for mandrel and spacer patterning
Patent Inventor Names
Anthony Yen
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Ming-Feng Shieh
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Shao-Ming Yu
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Shinn-Sheng Yu
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Chang-Yun Chang
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Clement Hsingjen Wann
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Jeff J. Xu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
8039179
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Patent Primary Examiner
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Christopher Young
0

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