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US Patent 8042087 Method to design network-on-chip (NOC)-based communication systems

Patent 8042087 was granted and assigned to École Polytechnique Fédérale de Lausanne on October, 2011 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Current Assignee
École Polytechnique Fédérale de Lausanne
École Polytechnique Fédérale de Lausanne
Date Filed
October 10, 2007
Date of Patent
October 18, 2011
Patent Application Number
12375525
Patent Citations Received
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US Patent 12135928 Constraints and objectives used in synthesis of a network-on-chip (NoC)
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US Patent 11836427 Constraints and objectives used in synthesis of a network-on-chip (NoC)
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US Patent 11956127 Incremental topology modification of a network-on-chip
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US Patent 12067335 Automatic configuration of pipeline modules in an electronics system
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US Patent 11657203 Multi-phase topology synthesis of a network-on-chip (NoC)
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US Patent 11675942 Optimization of parameters for synthesis of a topology using a discriminant function module
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US Patent 11748535 System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
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US Patent 11784909 Quality metrics for optimization tasks in generation of a network
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US Patent 11838211 System and method to determine optimal path(s) and use load balancing in an interconnect
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8042087
Patent Primary Examiner
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Helen Rossoshek

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