Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Raymond Filippi0
Indrajit Manna0
Lo Keng Foo0
Tan Pee Ya0
Date of Patent
March 13, 2012
Patent Application Number
12559401
Date Filed
September 14, 2009
Patent Citations Received
Patent Primary Examiner
Patent abstract
An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
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