Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Kunal R. Parekh0
Date of Patent
January 1, 2013
0Patent Application Number
131967610
Date Filed
August 2, 2011
0Patent Citations Received
Patent Primary Examiner
Patent abstract
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
