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US Patent 8561001 System and method for testing stacked dies
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Patent
Date Filed
July 11, 2012
Date of Patent
October 15, 2013
Patent Application Number
13546033
Patent Citations Received
US Patent 12025649 Integrated circuit die test architecture
0
US Patent 11762014 3D TAP and scan port architectures
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
8561001
Patent Primary Examiner
Phallaka Kik
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