Patent attributes
A ferroelectric memory device has word, bit, plate lines; memory cells having access gate and ferroelectric capacitor; latch amplifier for latching stored data; and write amplifier for driving bit lines according to write data. The bit lines are precharged to a reference potential before an active period. In active period, at a first time, selected word line and plate line are driven to a high-level potential so that ferroelectric capacitor output electric charge to selected bit line, and at a second time, selected bit line is brought to reference potential regardless of write data so that first data is written to selected memory cell, and at a third time, plate line is driven to reference potential and is maintained; and in a precharge period, the write amplifier drives selected bit line to high-level potential according to write data so that second data is written to selected memory cell.
