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US Patent 8709888 Hybrid CMOS nanowire mesh device and PDSOI device

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Patent Citations Received
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US Patent 12125916 Nanowire structures having non-discrete source and drain regions
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Patent Citations Received
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US Patent 11854905 Silicon and silicon germanium nanowire formation
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Patent abstract

A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.

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Patent Inventor Names
Chung-Hsun Lin0
Jeffrey W. Sleight0
Josephine B. Chang0
Leland Chang0
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US Patent 08709888 Hybrid CMOS nanowire mesh device and PDSOI device US Patent 8709888 Hybrid CMOS nanowire mesh device and PDSOI device

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Patent Number
087098880
Patent Number
87098880
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=087098880
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edited on 23 Apr, 2023
Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
087098880
Date of Patent
April 29, 2014
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Patent Application Number
133280690
Date Filed
December 16, 2011
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=087098880
Patent Primary Examiner
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Edward Wojciechowicz
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=08709888
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 US Patent 08709888 Hybrid CMOS nanowire mesh device and PDSOI device

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
08709888
Date of patent
April 29, 2014
Patent application number
13328069
Date Filed
December 16, 2011
Patent primary examiner
‌
Edward Wojciechowicz

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