US Patent 8710629 Apparatus and method for controlling semiconductor die warpage

A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die.