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US Patent 8728332 Methods of patterning small via pitch dimensions

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
May 7, 2012
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Date of Patent
May 20, 2014
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Patent Application Number
13465343
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Patent Citations Received
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US Patent 12074058 Patterning methods for semiconductor devices
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US Patent 11664237 Semiconductor device having improved overlay shift tolerance
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US Patent 11676821 Self-aligned double patterning
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US Patent 11699737 Integrated circuit with doped low-k side wall spacers for gate spacers
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US Patent 11748540 Method and structure for mandrel and spacer patterning
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US Patent 11749677 Semiconductor structure and methods of forming the same
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US Patent 11764286 Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
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US Patent 11784056 Self-aligned double patterning
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US Patent 11855226 Thin film transistor, semiconductor device and method of fabricating thin film transistor
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US Patent 11984355 Method for manufacturing an interconnection structure having a bottom via spacer
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•••
Patent Inventor Names
Dian-Hau Chen
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Yung-Shih Cheng
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Chih-Hao Hsieh
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Chung-Yi Lin
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Hsiang-Lin Chen
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Jiing-Feng Yang
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Ko-Bin Kao
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Tzu-Hao Huang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
8728332
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Patent Primary Examiner
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Roberts Culbert
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