US Patent 8729523 Three dimensional memory array architecture

Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of first conductive lines at a number of levels separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. The at least one conductive extension, storage element material, and cell select material are located between co-planar pairs of the plurality of first conductive lines.