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US Patent 8829676 Interconnect structure for wafer level package

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Is a

Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Date of Patent

September 9, 2014

Patent Application Number

13170973

Date Filed

June 28, 2011

Patent Citations Received

US Patent 12131984 Heterogeneous fan-out structure and method of manufacture

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US Patent 12125797 Package structure with fan-out feature

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US Patent 12125820 Through-dielectric vias for direct connection and method forming same

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US Patent 12132004 Semiconductor devices and methods of manufacture

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US Patent 11658085 Integrated circuit package and method

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US Patent 11670519 Redistribution structures for semiconductor packages and methods of forming the same

0

US Patent 11670601 Stacking via structures for stress reduction

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US Patent 11682626 Chamfered die of semiconductor package and method for forming the same

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Patent Primary Examiner

Julio J Maldonado

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