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US Patent 8829676 Interconnect structure for wafer level package
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Patent
Date Filed
June 28, 2011
Date of Patent
September 9, 2014
Patent Application Number
13170973
Patent Citations Received
US Patent 12131984 Heterogeneous fan-out structure and method of manufacture
0
US Patent 12125797 Package structure with fan-out feature
0
US Patent 12125820 Through-dielectric vias for direct connection and method forming same
0
US Patent 12132004 Semiconductor devices and methods of manufacture
0
US Patent 11658085 Integrated circuit package and method
0
US Patent 11670519 Redistribution structures for semiconductor packages and methods of forming the same
0
US Patent 11670601 Stacking via structures for stress reduction
0
US Patent 11682626 Chamfered die of semiconductor package and method for forming the same
0
US Patent 11682655 Semiconductor packages and methods of forming the same
0
US Patent 11749644 Semiconductor device with curved conductive lines and method of forming the same
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
8829676
Patent Primary Examiner
Julio J Maldonado
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