US Patent 8896126 Packaging DRAM and SOC in an IC package

US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging

US Patent 12001266 Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

US Patent 11841757 Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

US Patent 11844223 Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

US Patent 11836102 Low latency and high bandwidth artificial intelligence processor

US Patent 11791233 Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond

US Patent 11764190 3D stacked compute and memory with copper pillars

Patent

United States Patent and Trademark Office

Julio J Maldonado