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US Patent 8896126 Packaging DRAM and SOC in an IC package

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
August 21, 2012
Date of Patent
November 25, 2014
Patent Application Number
13590949
Patent Citations Received
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US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
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US Patent 12001266 Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic
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US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging
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US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic
0
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US Patent 11764190 3D stacked compute and memory with copper pillars
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US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond
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US Patent 11791233 Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
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US Patent 11836102 Low latency and high bandwidth artificial intelligence processor
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US Patent 11844223 Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
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US Patent 11841757 Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8896126
Patent Primary Examiner
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Julio J Maldonado

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