Patent attributes
A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.
