US Patent 9076686 Field effect transistor constructions and memory arrays

A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed.