US Patent 9123774 Semiconductor devices and methods of fabricating the same

Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.