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US Patent 9171627 Non-boosting program inhibit scheme in NAND design
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Patent
Date Filed
March 15, 2013
Date of Patent
October 27, 2015
Patent Application Number
13843642
Patent Citations Received
US Patent 12001684 Optimizing dynamic power loss protection adjustment in a storage system
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US Patent 11768763 Flash secure erase
US Patent 11947814 Optimizing resiliency group formation stability
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US Patent 11994723 Ribbon cable alignment apparatus
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US Patent 11681448 Multiple device IDs in a multi-fabric module storage system
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US Patent 11714572 Optimized data resiliency in a modular storage system
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
9171627
Patent Primary Examiner
Min Huang
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