US Patent 9171778 Dual-damascene process to fabricate thick wire structure
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Patent abstract
A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.
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US Patent 09171778 Dual-damascene process to fabricate thick wire structure US Patent 9171778 Dual-damascene process to fabricate thick wire structure
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Patent Number
091717780
Patent Number
91717780
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Patent Jurisdiction
Patent Number
091717780
Date of Patent
October 27, 2015
0Patent Application Number
141662740
Date Filed
January 28, 2014
0Official Website
Patent Primary Examiner
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US Patent 09171778 Dual-damascene process to fabricate thick wire structure
Infobox
Is a
Patent jurisdiction
Patent number
09171778
Date of patent
October 27, 2015
Patent application number
14166274
Date Filed
January 28, 2014
Patent primary examiner
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