US Patent 9209801 High frequency switch circuit including gate bias resistances

N (n is an integer more than one) number of transistors are connected in series in an order from a first transistor to an nth transistor from a first terminal to a second terminal. First to nth nodes are connected to gates of the first to nth transistors. N number of resistance elements are connected in series in an order from a first resistance element to an nth resistance element from a bias terminal to the nth node. The first resistance element is connected between said bias terminal and said first node, and the kth resistance element (k=2 to n) is connected between the (k−1)th node and the kth node. Thus, a high frequency switch circuit can reduce an area of the whole gate bias resistances.