US Patent 9236864 Stacked integrated circuit with redundancy in die-to-die interconnects

An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.