US Patent 9390808 Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell transistor and a word line connected to the memory cell transistor. A threshold voltage of the memory cell transistor is shifted to a negative voltage side by applying an erase pulse to the memory cell transistor. When the erase pulse is applied, if the threshold voltage of the memory cell transistor is higher than or equal to a first voltage, a second voltage is applied to the word line. If the threshold voltage of the memory cell transistor is lower than the first voltage and higher than or equal to a third voltage which is lower than the first voltage, a fourth voltage which is higher than the second voltage is applied to the word line.