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US Patent 9391041 Fan-out wafer level package structure

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
October 19, 2012
Date of Patent
July 12, 2016
Patent Application Number
13656053
Patent Citations Received
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US Patent 12062550 Molded direct contact interconnect substrate and methods of making same
0
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US Patent 11764117 Hermetically sealed optically transparent wafer-level packages and methods for making the same
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US Patent 11804443 Segregated power and ground design for yield improvement
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US Patent 11973051 Molded direct contact interconnect structure without capture pads and method for the same
0
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US Patent 11749534 Quad flat no-lead (QFN) package without leadframe and direct contact interconnect build-up structure and method for making the same
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9391041
Patent Primary Examiner
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Marc Armand

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