Is a
Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
January 24, 2017
Patent Application Number
15130166
Date Filed
April 15, 2016
Patent Citations Received
Patent Primary Examiner
Patent abstract
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.
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