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US Patent 9627365 Tri-layer CoWoS structure
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Edits on 30 Oct, 2024
"update inverses"
Golden AI
edited on 30 Oct, 2024
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Patent Citations Received
US Patent 12132029 Integrating passive devices in package structures
0
Edits on 9 Oct, 2024
"update inverses"
Golden AI
edited on 9 Oct, 2024
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Patent Citations Received
US Patent 12113056 Stacked dies and methods for forming bonded structures
0
Edits on 12 Sep, 2024
"update inverses"
Golden AI
edited on 12 Sep, 2024
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Patent Citations Received
US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
0
Edits on 5 Sep, 2024
"update inverses"
Golden AI
edited on 5 Sep, 2024
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+1
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Patent Citations Received
US Patent 12079475 Ferroelectric memory chiplet in a multi-dimensional packaging
0
Edits on 14 Aug, 2024
"update inverses"
Golden AI
edited on 14 Aug, 2024
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Patent Citations Received
US Patent 12062618 Chip package
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Edits on 24 Jul, 2024
"update inverses"
Golden AI
edited on 24 Jul, 2024
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Patent Citations Received
0
"update inverses"
Golden AI
edited on 24 Jul, 2024
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0
Edits on 4 Jul, 2024
"update inverses"
Golden AI
edited on 4 Jul, 2024
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Patent Citations Received
US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic
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Edits on 27 Jun, 2024
"update inverses"
Golden AI
edited on 27 Jun, 2024
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Patent Citations Received
US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging
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Edits on 6 Jun, 2024
"update inverses"
Golden AI
edited on 6 Jun, 2024
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Patent Citations Received
US Patent 12001266 Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic
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Edits on 22 May, 2024
"update inverses"
Golden AI
edited on 22 May, 2024
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Patent Citations Received
US Patent 11990427 Chiplet first architecture for die tiling applications
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Edits on 8 May, 2024
"update inverses"
Golden AI
edited on 8 May, 2024
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Patent Citations Received
US Patent 11978714 Encapsulated package including device dies connected via interconnect die
0
Edits on 1 May, 2024
"update inverses"
Golden AI
edited on 1 May, 2024
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Patent Citations Received
US Patent 11973041 Chiplet first architecture for die tiling applications
0
Edits on 10 Apr, 2024
"update inverses"
Golden AI
edited on 10 Apr, 2024
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Patent Citations Received
US Patent 11955463 Direct bonded stack structures for increased reliability and improved yield in microelectronics
0
Edits on 29 Mar, 2024
"update inverses"
Golden AI
edited on 29 Mar, 2024
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Patent Citations Received
US Patent 11942447 Storage layers for wafer bonding
0
Edits on 21 Mar, 2024
"update inverses"
Golden AI
edited on 21 Mar, 2024
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Patent Citations Received
US Patent 11935907 Image sensor device
0
Edits on 9 Feb, 2024
"update inverses"
Golden AI
edited on 9 Feb, 2024
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Patent Citations Received
US Patent 11894306 Chip package
0
Edits on 13 Dec, 2023
"update inverses"
Golden AI
edited on 13 Dec, 2023
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Patent Citations Received
US Patent 11841757 Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic
0
"update inverses"
Golden AI
edited on 13 Dec, 2023
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Patent Citations Received
US Patent 11844223 Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
0
Edits on 7 Dec, 2023
"update inverses"
Golden AI
edited on 7 Dec, 2023
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Patent Citations Received
US Patent 11836102 Low latency and high bandwidth artificial intelligence processor
0
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