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US Patent 9627365 Tri-layer CoWoS structure

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
January 27, 2016
Date of Patent
April 18, 2017
Patent Application Number
15007714
Patent Citations Received
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US Patent 12132029 Integrating passive devices in package structures
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US Patent 12079475 Ferroelectric memory chiplet in a multi-dimensional packaging
0
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US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
0
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US Patent 12113056 Stacked dies and methods for forming bonded structures
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US Patent 11749610 Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
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US Patent 11764177 Bonded structure with interconnect structure
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US Patent 11764190 3D stacked compute and memory with copper pillars
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US Patent 11769735 Chiplet first architecture for die tiling applications
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US Patent 11769724 Package having different metal densities in different regions and manufacturing method thereof
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US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond
•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9627365
Patent Primary Examiner
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Thien F. Tran

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