Patent attributes
An integrated circuit includes first and second SRAM cells. The first SRAM cell includes first and second pull-up devices, first and second pull-down devices configured with the first and second pull-up devices to form first and second cross-coupled inverters, first and second pass-gate devices configured with the first and second cross-coupled inverters for writing data, a read pull-down device coupled to the first inverter, and a read pass-gate device coupled to the read pull-down device. The second SRAM cell includes third and fourth pull-up devices, and third and fourth pull-down devices configured with the third and fourth pull-up devices to form third and fourth cross-coupled inverters. Work function layers of gates of the first pull-up device, first pull-down device, and third pull-up device have a first work function, a second work function, and a third work function respectively. The first, second, and third work functions are different from each other.
