Patent attributes
A dual-port static random access memory (SRAM) cell includes first through third power lines, a storage unit connected to the first through third power lines, a first port having first and second pass-gate transistors controlled by a first wordline, a second port having third and fourth pass-gate transistors controlled by a second wordline, and first through fourth bitlines coupled to the storage unit through the first through fourth pass-gate transistors, respectively. The first through fourth bitlines and the first through third power lines each extend in a first direction and are formed of a first metal layer. The first wordline extends in a second direction substantially perpendicular to the first direction and is formed of a second metal layer above the first metal layer. The second wordline extends in the second direction and is formed of a upper-level metal layer above the second metal layer.
