US Patent 9748359 Vertical transistor bottom spacer formation

A silicon layer is formed on a surface of each bottom source/drain region that is present at the footprint of a semiconductor fin. A first set of atoms (nitrogen atoms or carbon atoms) and a second set of atoms (boron atoms and/or carbon atoms) are then ion implanted into the silicon layer and the bottom source/drain regions. An anneal is then performed to convert the silicon layer into a bottom dielectric spacer that is composed of a reaction product of silicon, the first set of atoms and the second set of atoms, while converting each bottom source/drain region into a bottom source/drain structure that includes a first region and a second region. The second region is composed of a doped semiconductor material and at least one of the boron atoms and the carbon atoms; no measurable nitrogen tail and/or oxygen tail is present in the source/drain structures.