Is a
Patent attributes
Patent Applicant
Patent Jurisdiction
Patent Number
Patent Inventor Names
Anurag Jindal0
Sagar Kataria0
Mayank Parasrampuria0
Date of Patent
September 19, 2017
0Patent Application Number
148757170
Date Filed
October 6, 2015
0Patent Citations Received
Patent Primary Examiner
Patent abstract
An integrated circuit (IC) includes a logic built-in self-test (LBIST) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. A debug controller receives the scan out signals and shifts a set of the scan out signals to a joint test action group (JTAG) controller. The debug controller also maintains a dynamic count indicative of the number of debug shift operations performed, and compares the dynamic count with a final count. If the dynamic count is less than the final count, the debug controller performs a second debug shift operation, which facilitates determination of a fault location in the IC.
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