US Patent 9842914 Nanosheet FET with wrap-around inner spacer

A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack disposed above a substrate; forming a top sacrificial layer on a top surface of the nanosheet stack; forming a sidewall sacrificial layer on two opposite sidewalls of the nanosheet stack, such that a first and a second end of a first vertically-stacked nanosheet are exposed; removing the sidewall sacrificial layer, a portion of a first and a second end of a first sacrificial layer, and a portion of a first and a second end of a top sacrificial layer to expose portions of the first vertically-stacked nanosheet; and forming an inner spacer region on the first vertically-stacked nanosheet to replace the removed sidewall sacrificial layer, the removed portions of the first sacrificial layer, and the removed portions of the top sacrificial layer.