Patent attributes
A method of designing a layout of a metallization stack of an integrated circuit (IC), where the stack includes metal layers having patterned metal features. The method includes determining a layout of a first grid of the metallization stack, including patterned metal features for supplying power and providing signal connections to components of the IC. The method also includes determining a layout of a second grid of the stack for securing the IC against electromagnetic attacks. The second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack. The patterned metal features of the second grid are electrically connected to the first grid. The method further includes determining at least one layout change for the metallization stack in accordance with an engineering change order.
