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US Patent 9911497 Three-dimensional vertical NOR flash thin-film transistor strings

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Date Filed
October 13, 2017
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Date of Patent
March 6, 2018
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Patent Application Number
15783201
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Patent Citations Received
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US Patent 11675500 High capacity memory circuit with low effective latency
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US Patent 11705496 Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array
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US Patent 11710729 Wafer bonding in fabrication of 3-dimensional NOR memory circuits
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US Patent 11749344 Three-dimensional vertical nor flash thin-film transistor strings
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US Patent 11751388 3-dimensional nor strings with segmented shared source regions
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US Patent 11751391 Methods for fabricating a 3-dimensional memory structure of nor memory strings
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US Patent 11751392 Fabrication method for a 3-dimensional NOR memory array
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US Patent 11758727 Three-dimensional vertical nor flash thin-film transistor strings
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US Patent 12068286 Device with embedded high-bandwidth, high-capacity memory using wafer bonding
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US Patent 11789644 Memory centric system incorporating computational memory
•••
Patent Inventor Names
Eli Harari
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
9911497
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Patent Primary Examiner
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Harry W Byrne
0

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