US Patent 9985075 Dummy bottom electrode in interconnect to reduce CMP dishing

The present disclosure relates an integrated circuit (IC). A plurality of metal layers is disposed within an inter-layer dielectric (ILD) material over the substrate. A memory cell is disposed over a first metal layer at a memory region and comprising a bottom electrode directly above a first metal line within the first metal layer and a top electrode separated from the bottom electrode by a resistance switching element. A dummy structure comprises a dummy bottom electrode arranged directly above a second metal line within the first metal layer at a logic region adjacent to the memory region.