US Patent RE39895 Semiconductor integrated circuit arrangement fabrication method
Patent RE39895 was granted and assigned to Renesas Technology Corp on October, 2007 by the United States Patent and Trademark Office.
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Patent Inventor Names
Hideyuki Kazumi0
Kazutami Tago0
Ken Yoshioka0
Sadayuki Okudaira0
Takafumi Tokunaga0
Tatsumi Mizutani0
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Patent abstract
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
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US Patent RE039895 Semiconductor integrated circuit arrangement fabrication method US Patent RE39895 Semiconductor integrated circuit arrangement fabrication method
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Patent Number
RE0398950
Patent Number
RE398950
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Is a
Current Assignee
0
Patent Jurisdiction
Patent Number
RE0398950
Date of Patent
October 23, 2007
0Patent Application Number
100941570
Date Filed
March 8, 2002
0Official Website
Patent Primary Examiner
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US Patent RE039895 Semiconductor integrated circuit arrangement fabrication method
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
RE039895
Date of patent
October 23, 2007
Patent application number
10094157
Date Filed
March 8, 2002
Patent primary examiner
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