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Thanhha S. Pham

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Edits on 2 Sep, 2022
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Megan Gustafson
edited on 2 Sep, 2022
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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7115509 Method for forming polysilicon local interconnects
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US Patent 7126224 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements
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US Patent 7129128 Method of improved high K dielectric-polysilicon interface for CMOS devices
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US Patent 7132749 Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment
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US Patent 7135360 Liquid crystal display device and method of fabricating the same
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US Patent 7135361 Method for fabricating transistor gate structures and gate dielectrics thereof
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US Patent 7138313 Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing
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US Patent 7138702 Integrated circuit chip
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US Patent 7141469 Method of forming poly insulator poly capacitors by using a self-aligned salicide process
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US Patent 7141886 Air pocket resistant semiconductor package
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US Patent 7144786 Technique for forming a transistor having raised drain and source regions with a reduced number of process steps
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US Patent 7148099 Reducing the dielectric constant of a portion of a gate dielectric
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US Patent 7151022 Methods for forming shallow trench isolation
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US Patent 7153775 Conductive material patterning methods
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US Patent 7154185 Encapsulation method for SBGA
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US Patent 7157772 Semiconductor device and method of fabricating the same
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US Patent 7157778 Semiconductor constructions
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US Patent 7161204 DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area
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US Patent 7166497 Electronic component package and method of manufacturing same
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US Patent 7173337 Semiconductor device manufactured by the damascene process having improved stress migration resistance
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US Patent 7176132 Manufacturing method of semiconductor device
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US Patent 7180163 Support with integrated deposit of gas absorbing material for manufacturing microelectronic, microoptoelectronic or micromechanical devices
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US Patent 7183650 Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate
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US Patent 7186603 Method of forming notched gate structure
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US Patent 7186640 Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics
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US Patent 7186642 Low temperature nitride used as Cu barrier layer
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US Patent 7192881 Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity
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US Patent 7196380 High mobility plane FinFET with equal drive strength
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US Patent 7198994 Semiconductor device and manufacturing method of semiconductor device
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US Patent 7202156 Process for manufacturing a wiring substrate
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US Patent 7205189 Method of manufacturing a dual bit flash memory
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US Patent 7205212 Device transferring method
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US Patent 7205213 Device transferring method
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US Patent 7205214 Device transferring method
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US Patent 7208346 Methods of forming interposers on surfaces of dies of a wafer
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US Patent 7208356 Method of manufacturing multiple-gate MOS transistor having an improved channel structure
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US Patent 7208413 Formation of boride barrier layers using chemisorption techniques
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US Patent 7211511 Method for manufacturing a magnetic memory device
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US Patent 7217638 Wafer back surface treating method and dicing sheet adhering apparatus
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US Patent 7217970 Devices containing platinum-iridium films and methods of preparing such films and devices
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US Patent 7220631 Method for fabricating semiconductor device having high withstand voltage transistor
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US Patent 7220654 Method for manufacturing semiconductor substrate
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US Patent 7224224 Thin film semiconductor device and manufacturing method
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US Patent 7235439 Method of forming a MOS-controllable power semiconductor device for use in an integrated circuit
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US Patent 7238560 Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
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US Patent 7238565 Methodology for recovery of hot carrier induced degradation in bipolar devices
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US Patent 7244967 Apparatus and method for attaching an integrating circuit sensor to a substrate
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US Patent 7247915 Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology
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US Patent 7250319 Method of fabricating quantum features
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US Patent 7253099 Method of manufacturing semiconductor device that includes forming self-aligned contact pad
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US Patent 7253113 Methods for using a silylation technique to reduce cell pitch in semiconductor devices
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US Patent 7253487 Integrated circuit chip having a seal ring, a ground ring and a guard ring
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US Patent 7253502 Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same
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US Patent 7256078 High mobility plane FinFETs with equal drive strength
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US Patent 7256101 Methods for preparing a semiconductor assembly
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US Patent 7259025 Ferromagnetic liner for conductive lines of magnetic memory cells
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US Patent 7259424 Semiconductor device having a trench with a step-free insulation film
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US Patent 7265437 Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties
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US Patent 7271442 Transistor structure having stressed regions of opposite types underlying channel and source/drain regions
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US Patent 7273776 Methods of forming a P-well in an integrated circuit device
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US Patent 7282396 Method of manufacturing a semiconductor device including using a sealing resin to form a sealing body
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US Patent 7282418 Method for fabricating a self-aligned bipolar transistor without spacers
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US Patent 7288421 Method for forming an optoelectronic device having an isolation layer
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US Patent 7288446 Single and double-gate pseudo-FET devices for semiconductor materials evaluation
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US Patent 7291539 Amorphization/templated recrystallization method for hybrid orientation substrates
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US Patent 7297582 Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions
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US Patent 7297998 Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same
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US Patent 7300867 Dual damascene interconnect structures having different materials for line and via conductors
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US Patent 7307015 Method for forming an interconnection line in a semiconductor device
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US Patent 7319258 Semiconductor-on-insulator chip with<100>-oriented transistors
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US Patent 7326643 Method of making circuitized substrate with internal organic memory device
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US Patent 7329555 Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process
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US Patent 7329565 Silicide-silicon oxide-semiconductor antifuse device and method of making
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US Patent 7332406 Air gap interconnect structure and method
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US Patent 7332774 Multiple-gate MOS transistor and a method of manufacturing the same
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US Patent 7335917 Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor
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US Patent 7338842 Process for exposing solder bumps on an underfill coated semiconductor
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US Patent 7339204 Backside contact for touchchip
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US Patent 7348666 Chip-to-chip trench circuit structure
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US Patent 7351604 Microstructures
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US Patent 7352065 Semiconductor devices having amorphous silicon-carbon dielectric and conducting layers
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US Patent 7354863 Methods of selectively removing silicon
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US Patent 7355253 Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
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US Patent 7358180 Method of forming wiring structure and semiconductor device
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US Patent 11180861 3-dimensional NOR string arrays in segmented stacks
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US Patent 7365354 Programmable resistance memory element and method for making same
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US Patent 7368395 Method for fabricating a nano-imprinting mold
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US Patent 7368812 Interposers for chip-scale packages and intermediates thereof
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US Patent 7371607 Method of manufacturing semiconductor device and method of manufacturing electronic device
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US Patent 7371610 Process for fabricating an integrated circuit package with reduced mold warping
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US Patent 7371613 Semiconductor device and method of manufacturing the same
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US Patent 7371633 Dielectric layer for semiconductor device and method of manufacturing the same
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US Patent 7378314 Source side injection storage device with control gates adjacent to shared source/drain and method therefor
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US Patent 7384803 Method of manufacturing nitride semiconductor device including SiC substrate and apparatus for manufacturing nitride semiconductor device
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US Patent 7384857 Method to fabricate completely isolated silicon regions
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US Patent 7427565 Multi-step etch for metal bump formation
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US Patent 11189558 Process to yield ultra-large integrated circuits and associated integrated circuits
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US Patent 11189633 Semiconductor device and apparatus of manufacturing the same
Edits on 2 Dec, 2021
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Golden AI
edited on 2 Dec, 2021
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Patent primary examiner of
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US Patent 11189633 Semiconductor device and apparatus of manufacturing the same
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Golden AI
edited on 2 Dec, 2021
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Infobox (+1 properties)
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Patent primary examiner of
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US Patent 11189558 Process to yield ultra-large integrated circuits and associated integrated circuits
Edits on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
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Patent primary examiner of
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US Patent 7427565 Multi-step etch for metal bump formation
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7384857 Method to fabricate completely isolated silicon regions
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Golden AI
edited on 30 Nov, 2021
Edits on 29 Nov, 2021
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Golden AI
edited on 29 Nov, 2021
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7371633 Dielectric layer for semiconductor device and method of manufacturing the same
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Golden AI
edited on 26 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7371613 Semiconductor device and method of manufacturing the same
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Golden AI
edited on 26 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7371610 Process for fabricating an integrated circuit package with reduced mold warping
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Golden AI
edited on 26 Nov, 2021
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368812 Interposers for chip-scale packages and intermediates thereof
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368395 Method for fabricating a nano-imprinting mold
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7365354 Programmable resistance memory element and method for making same
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 11180861 3-dimensional NOR string arrays in segmented stacks
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358180 Method of forming wiring structure and semiconductor device
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Golden AI
edited on 25 Nov, 2021
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7354863 Methods of selectively removing silicon
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7352065 Semiconductor devices having amorphous silicon-carbon dielectric and conducting layers

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