US Patent 10050045 SRAM cell with balanced write port

An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.