US Patent 11374088 Leakage reduction in gate-all-around devices

A semiconductor device includes a substrate; a well of a first conductivity-type and including an anti-punch-through (APT) layer of the first conductivity-type; source and drain features of a second conductivity-type over the APT layer; a strap feature of the first conductivity-type over the well; multiple vertically-stacked channel layers over the APT layer and connecting the source and drain features; a gate wrapping around each channel layer; source and drain contacts electrically coupled to the source and drain features; source and drain vias landed on the source and drain contacts; a strap contact electrically coupled to the strap feature; and a strap via landed on the strap contact. The source via and the strap via are configured to be coupled to different voltages during a non-active mode of the semiconductor device and to be coupled to a substantially same voltage during an active mode of the semiconductor device.