US Patent 10075173 Digital fast lock for phase-locked loops

A phase-locked loop uses an edge detect circuit to detect an edge of an input clock signal. The detected edge is used to digitally align an initial edge of the feedback signal with the input clock signal to the PLL so that the feedback signal is substantially aligned with the input clock signal. The edge alignment of the feedback signal may be performed at startup or in response to loss of lock/input clock switching. By aligning the feedback signal the input clock signal based on the edge detect, faster lock occurs.