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US Patent 10103238 Nanosheet field-effect transistor with full dielectric isolation
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Date Filed
July 18, 2017
Date of Patent
October 16, 2018
Patent Application Number
15652890
Patent Citations Received
US Patent 11862634 Nanostructure with various widths
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US Patent 10892326 Removal of a bottom-most nanowire from a nanowire device stack
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US Patent 10957761 Electrical isolation for nanosheet transistor devices
US Patent 11062937 Dielectric isolation for nanosheet devices
US Patent 11075301 Nanosheet with buried gate contact
US Patent 11295983 Transistor having source or drain formation assistance regions with improved bottom isolation
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US Patent 11682591 Method for forming transistor structures
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US Patent 11362001 Method for manufacturing nanostructures with various widths
US Patent 11380591 Method for manufacturing nanostructure with various widths
US Patent 11393925 Semiconductor device structure with nanostructure
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•••
Patent Inventor Names
Ruilong Xie
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Tek Po Rinus Lee
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Chanro Park
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Haigou Huang
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Hui Zang
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Min Gyu Sung
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Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10103238
Patent Primary Examiner
Eric Ward
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