US Patent 11862634 Nanostructure with various widths

A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.