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US Patent 10116315 System-on-a-chip clock phase management using fractional-N PLLs

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US Patent 12063049 Time-to-digital converter and calibration
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Patent abstract

A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.

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US Patent 11711084 Phase lock loop (PLL) synchronization
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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
101163150
Date of Patent
October 30, 2018
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Patent Application Number
157119180
Date Filed
September 21, 2017
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Patent Citations Received
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US Patent 10425086 Divider-less phase locked loop
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US Patent 10784844 Fractional frequency divider and frequency synthesizer
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US Patent 11296860 Phase-aligning multiple synthesizers
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Patent Primary Examiner
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Phuong Phu
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US Patent 11296860 Phase-aligning multiple synthesizers
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US Patent 10784844 Fractional frequency divider and frequency synthesizer
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US Patent 10425086 Divider-less phase locked loop
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 US Patent 10116315 System-on-a-chip clock phase management using fractional-N PLLs

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10116315
Date of patent
October 30, 2018
Patent application number
15711918
Date Filed
September 21, 2017
Patent primary examiner
‌
Phuong Phu

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