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US Patent 10116315 System-on-a-chip clock phase management using fractional-N PLLs

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
September 21, 2017
Date of Patent
October 30, 2018
Patent Application Number
15711918
Patent Citations Received
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US Patent 12063049 Time-to-digital converter and calibration
0
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US Patent 11509410 Method for a slave device for calibrating its output timing, method for a master device for enabling a slave device to calibrate its output timing, master device and slave device
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US Patent 11296860 Phase-aligning multiple synthesizers
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US Patent 11711084 Phase lock loop (PLL) synchronization
0
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US Patent 11509312 Apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops
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US Patent 10425086 Divider-less phase locked loop
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US Patent 10784844 Fractional frequency divider and frequency synthesizer
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10116315
Patent Primary Examiner
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Phuong Phu

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