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US Patent 10269768 Stacked integrated circuits with redistribution lines
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Patent
Date Filed
September 19, 2016
Date of Patent
April 23, 2019
Patent Application Number
15269431
Patent Citations Received
US Patent 12113005 Packages with Si-substrate-free interposer and method forming same
0
US Patent 11610858 Packages with Si-substrate-free interposer and method forming same
0
US Patent 11769718 Packages with Si-substrate-free interposer and method forming same
US Patent 11469166 Packages with Si-substrate-free interposer and method forming same
US Patent 11527465 Packages with Si-substrate-free interposer and method forming same
US Patent 10685910 Packages with Si-substrate-free interposer and method forming same
US Patent 10748841 Packages with Si-substrate-free interposer and method forming same
US Patent 10854568 Packages with Si-substrate-free interposer and method forming same
US Patent 10971443 Packages with Si-substrate-free interposer and method forming same
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10269768
Patent Primary Examiner
Tom Thomas
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