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US Patent 10319699 Chip package having die structures of different heights

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
October 16, 2017
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Date of Patent
June 11, 2019
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Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Application Number
15784807
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Patent Citations
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US Patent 10026724 Semiconductor package and method of manufacturing the same
Patent Citations Received
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US Patent 12113005 Packages with Si-substrate-free interposer and method forming same
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US Patent 10748841 Packages with Si-substrate-free interposer and method forming same
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US Patent 10854568 Packages with Si-substrate-free interposer and method forming same
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US Patent 10971443 Packages with Si-substrate-free interposer and method forming same
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US Patent 11069657 Chip package having die structures of different heights and method of forming same
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US Patent 11610858 Packages with Si-substrate-free interposer and method forming same
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US Patent 11282759 Chip package structure having warpage control and method of forming the same
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US Patent 11769718 Packages with Si-substrate-free interposer and method forming same
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US Patent 12087729 Multi-chip package having stress relief structure
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US Patent 11469166 Packages with Si-substrate-free interposer and method forming same
•••
Patent Inventor Names
Chi-Hsi Wu
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Weiming Chris Chen
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Wen-Hsin Wei
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Chen-Hua Yu
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Hsien-Pin Hu
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Shang-Yun Hou
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10319699
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Patent Primary Examiner
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Alexander O Williams
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