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US Patent 10366930 Self-aligned gate cut isolation

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
June 11, 2018
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Date of Patent
July 30, 2019
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Patent Application Number
16005064
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Patent Citations Received
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US Patent 12027608 Semiconductor structure having dielectric structure extending into second cavity of semiconductor Fin
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US Patent 10629701 Self-aligned gate cut method and multilayer gate-cut pillar structure
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US Patent 10714591 Gate structure for a transistor device with a novel pillar structure positioned thereabove
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US Patent 11955483 Semiconductor device and fabrication method thereof
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Patent Inventor Names
Ruilong Xie
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Chanro Park
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Guillaume Bouche
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Kangguo Cheng
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Min Gyu Sung
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10366930
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Patent Primary Examiner
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Feifei Yeung Lopez
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