US Patent 10497796 Vertical transistor with reduced gate length variation

Techniques for reducing gate length variation in VFET devices are provided. In one aspect, a method for forming a VFET device includes: forming a first and a second semiconductor layer as a stack on a substrate; patterning fins in the stack each of which extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins include active fin channels; selectively thinning the active fin channels; forming sidewall spacers alongside the active fin channels; forming bottom source and drains at a base of the fins below the sidewall spacers; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers; forming top spacers on the gate stacks; and forming top source and drains on the top spacers. A VFET device is also provided.